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Image reconstruction analysis for positron emission tomography with heterostructured scintillators
(2022)
The concept of structure engineering has been proposed for exploring the next generation of radiation detectors with improved performance. A TOF-PET geometry with heterostructured scintillators with a pixel size of 3.0×3.1×15 mm3 was simulated using Monte Carlo. The heterostructures consisted of alternating layers of BGO as a dense material with high stopping power and plastic (EJ232) as a fast light emitter. The detector time resolution was calculated as a function of the deposited and shared energy in both materials on an event-by-event basis. While sensitivity was reduced to 32% for 100 μm thick plastic layers and 52% for 50 μm, the CTR distribution improved to 204±49 ps and 220±41 ps respectively, compared to 276 ps that we considered for bulk BGO. The complex distribution of timing resolutions was accounted for in the reconstruction. We divided the events into three groups based on their CTR and modeled them with different Gaussian TOF kernels. On a NEMA IQ phantom, the heterostructures had better contrast recovery in early iterations. On the other hand, BGO achieved a better contrast to noise ratio (CNR) after the 15th iteration due to the higher sensitivity. The developed simulation and reconstruction methods constitute new tools for evaluating different detector designs with complex time responses.
In our case the double-side-method is used to minimize the complexity of a matrix-readout. Here the number of channels is reduced to 2√N̅. It is also possible to benefit from the method in a single pixel readout system. One signal can be used to measure position and energy of the event, the other one can be applied to a fast trigger-circuit at the same time. In a next step we will investigate timing behavior and electrical crosstalk of the circuit.
The readout of gamma detectors is considerably simplified when the event intensity is encoded as a pulse width (Pulse Width Modulation, PWM). Time-to-Digital-Converters (TDC) replace the conventional ADCs and multiple TDCs can be realized easily in one PLD chip (Programmable Logic Device). The output of a PWM stage is only one digital signal per channel which is well suited for transport so that further processing can be performed apart from the detector. This is particularly interesting for large systems with high channel density (e.g. high resolution scanners). In this work we present a circuit with a linear transfer function that requires a minimum of components by performing the PWM already in the preamp stage. This allows a very compact and also cost-efficient implementation of the front-end electronics.