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- Fachbereich Medizintechnik und Technomathematik (1299)
- INB - Institut für Nano- und Biotechnologien (484)
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Within the developments for the Crystal Clear small animal PET project (CLEARPET) a dual head PET system has been established. The basic principle is the early digitization of the detector pulses by free running ADCs. The determination of the γ-energy and also the coincidence detection is performed by data processing of the sampled pulses on the host computer. Therefore a time mark is attached to each pulse identifying the current cycle of the 40 MHz sampling clock. In order to refine the time resolution the pulse starting time is interpolated from the samples of the pulse rise. The detector heads consist of multichannel PMTs with a single LSO scintillator crystal coupled to each channel. For each PMT only one ADC is required. The position of an event is obtained separately from trigger signals generated for each single channel. An FPGA is utilized for pulse buffering, generation of the time mark and for the data transfer to the host via a fast I/O-interface.
A small PET system has been built up with two multichannel photomultipliers, which are attached to a matrix of 64 single LSO crystals each. The signal from each multiplier is being sampled continuously by a 12 bit ADC at a sampling frequency of 40 MHz. In case of a scintillation pulse a subsequent FPGA sends the corresponding set of samples together with the channel information and a time mark to the host computer. The data transfer is performed with a rate of 20 MB/s. On the host all necessary information is extracted from the data. The pulse energy is determined, coincident events are detected and multiple hits within one matrix can be identified. In order to achieve a narrow time window the pulse starting time is refined further than the resolution of the time mark (=25 ns) would allow. This is possible by interpolating between the pulse samples. First data obtained from this system will be presented. The system is part of developments for a much larger system and has been created to study the feasibility and performance of the technique and the hardware architecture.